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M48T128Y M48T128V
3.3V-5V 1 Mbit (128Kb x8) TIMEKEEPER(R) SRAM
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INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, AND CRYSTAL BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T128Y: 4.1V VPFD 4.5V - M48T128V: 2.7V VPFD 3.0V
32 1
s
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CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES SOFTWARE CONTROLLED CLOCK CALIBRATION for HIGH ACCURACY APPLICATIONS 10 YEARS of DATA RETENTION and CLOCK OPERATION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 128K X 8 SRAMS SELF-CONTAINED BATTERY and CRYSTAL in DIP PACKAGE
A0-A16
PMDIP32 (PM) Module
s
Figure 1. Logic Diagram
s
s
VCC
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17
8 DQ0-DQ7 M48T128Y M48T128V
Table 1. Signal Names
A0-A16 DQ0-DQ7 E G W VCC VSS NC Address Inputs Data Inputs / Outputs Chip Enable Input Output Enable Input Write Enable Input Supply Voltage Ground Not Connected Internally
W E G
VSS
AI02244
March 2000
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M48T128Y, M48T128V
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation M48T128Y M48T128V Value 0 to 70 -40 to 70 -0.3 to VCC+0.3 -0.3 to 7.0 -0.3 to 4.6 20 1 Unit C C V V V mA W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
Figure 2. DIP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
32 1 31 2 30 3 29 4 28 5 27 6 26 7 8 M48T128Y 25 9 M48T128V 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16
AI02245
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
DESCRIPTION The M48T128Y/V TIMEKEEPER RAM is a 128Kb x 8 non-volatile static RAM and real time clock. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. The M48T128Y/V directly replaces industry standard 128Kb x 8 SRAM.
It also provides the non-volatility of Flash without any requirement for special write timing or limitations on the number of writes that can be performed. The 32 pin 600 mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. Figure 3 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 1FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations consisting of BiPORTTM read/write memory cells within the static RAM array. The M48T128Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T128Y/V also has its own PowerFail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
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M48T128Y, M48T128V
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO
(2) (2)
VCC 4.5V to 5.5V or 3.0V to 3.6V
E VIH VIL VIL VIL X X
G X X VIL VIH X X
W X VIL VIH VIH X X
DQ0-DQ7 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
READ MODE The M48T128Y/V is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access. WRITE MODE The M48T128Y/V is in the Write Mode whenever W (Write Enable) and E (Chip Enable) are low state after the address inputs are stable. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 3. AC Testing Load Circuit (2)
DEVICE UNDER TEST
650
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
Note: 1. 50pF for M48T128V (3.3V). 2. Excluding open drain output pins.
DATA RETENTION MODE With valid V CC applied, the M48T128Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "don't care".
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M48T128Y, M48T128V
Figure 4. Block Diagram
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8x8 TIMEKEEPER REGISTERS A0-A16
131,064 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
VSS
AI01804
Note: A power failure during a write cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the V CC fall time is not less than tF. The M48T128Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When V CC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T128Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above V SO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max).
CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control Register (1FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second after the READ bit is reset to a '0'.
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M48T128Y, M48T128V
Table 5. Capacitance (1) (TA = 25 C, f = MHz)
Symbol CIN CIO (2) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 20 20 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Outputs deselected.
Table 6A. DC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC -0.2V -0.3 2.2 Min Max 2 2 95 8 4 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
Table 6B. DC Characteristics (TA = 0 to 70 C; VCC = 3.0V to 3.6V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.2 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC -0.2V -0.3 2.2 Min Max 2 2 50 4 3 0.4 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
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M48T128Y, M48T128V
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSS tF tFB INPUTS
RECOGNIZED
tR tRB DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI03612
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C)
Symbol VPFD Parameter M48T128Y Power-fail Deselect Voltage M48T128V M48T128Y VSO tDR (2) Battery Back-up Switchover Voltage M48T128V Expected Data Retention Time 10 VPFD -100mV V YEARS 2.7 2.9 3.0 3.0 V V Min 4.1 Typ 4.35 Max 4.5 Unit V
Note: 1. All voltages referenced to VSS. 2. At 25C.
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C)
Symbol tF (1) tFB (2) tR tRB tREC Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to Inputs Recognized Min 300 10 0 1 40 200 Max Unit s s s s ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 50s after VCC passes VPFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
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M48T128Y, M48T128V
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C)
M48T128Y Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 5 70 70 70 40 5 5 30 30 -70 Max Min 85 85 85 55 M48T128V -85 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF or 50pF (See Figure 3). 2. CL = 5pF.
Figure 6. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV tAXQX DQ0-DQ7 DATA VALID DATA VALID VALID
AI02324
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M48T128Y, M48T128V
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C)
M48T128Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 60 60 5 70 0 0 50 55 5 10 30 30 5 10 25 70 70 5 -70 Max Min 85 0 0 60 65 5 15 35 35 5 15 30 M48T128V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Setting the Clock Bit D7 of the Control Register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11). Resetting the WRITE bit to a '0' then transfers the values of all time registers 1FFFFh-1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur one second later.
Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at Bit D7 within 1FFF9h. Setting it to a '1' stops the oscillator. The M48T128Y/V is shipped from STMicroelectronics with the STOP bit set to a '1'. When reset to a '0', the M48T128Y/ V oscillator starts after one second.
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M48T128Y, M48T128V
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
VALID tAXQX tEHQZ
tGHQZ
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02382
tWHAX
tWHQX
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M48T128Y, M48T128V
Figure 9. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tAVWL W tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02383
tELEH
tEHAX
CALIBRATING THE CLOCK The M48T128Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +4 ppm at 25C. The oscillation rate of crystals changes with temperature. The M48T128Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in Figure 10. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Figure 10 illustrates a TIMEKEEPER calibration waveform. One method is available for ascertaining how much calibration a given M48T128Y/V may require. This involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in STMicroelectronics Application Note: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. For example, a deviation of 21 seconds slow over a period of 30 days would indicate a -8 ppm oscillator frequency error, requiring a +2(WR100010) to be loaded into the Calibration Byte for correction.
10/14
M48T128Y, M48T128V
Table 11. Register Map
Data Address D7 1FFFFh 1FFFEh 1FFFDh 1FFFCh 1FFFBh 1FFFAh 1FFF9h 1FFF8h
Keys:
D6
D5
D4
D3
D2 Year
D1
D0
Function/Range BCD Format Year Month Date 00-99 01-12 01-31 01-07 00-23 00-59 00-59
10 Years 0 0 0 0 0 ST W R 0 0 0 0 0 10 M.
Month Date 0 Day Hours Minutes Seconds Calibration
10 Date 0 0
Day Hour Minutes Seconds Control
10 Hours 10 Minutes 10 Seconds S
S = SIGN Bit R = READ Bit W = WRITE Bit ST = STOP Bit
0 = Must be set to zero Z = '0' and are Read only Y = '1' or '0'
Figure 10. Calibration Waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION Note: ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F is recommended in order to provide the needed filtering. In
addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount).
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M48T128Y, M48T128V
Table 12. Ordering Information Scheme
Example: Device Type M48T Supply Voltage and Write Protect Voltage Y = VCC = 4.5V to 5.5V; VPFD = 4.1V to 4.5V V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V Speed -70 = 70ns -85 = 85ns Package PM = PMDIP32 Temperature Range 1 = 0 to 70 C M48T128Y -70 PM 1
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 13. Revision History
Date June 1998 01/31/00 03/30/00 First Issue Calibrating The Clock Paragraph changed Storage Temperature changed (Table 2) Revision Details
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M48T128Y, M48T128V
Table 14. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm Symbol Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Drawing is not to scale.
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M48T128Y, M48T128V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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